M.N.I.A Aziz, F. Salehuddin, A.S.M. Zain, K.E. Kaharudin


Silicon-on-insulator (SOI) technology is an effective approach of mitigating the short channel effect (SCE) problems. The SOI is believed to be capable of suppressing the SCE, thereby improving the overall electrical characteristics of MOSFET device. SCE in SOI MOSFET is heavily influenced by thin film thickness, thin-film doping density and buried oxide (BOX) thickness. This paper will analyze the effect of BOX towards SOI MOSFET device. The 50nm and 10nm thickness of buried oxide in SOI MOSFET was developed by using SILVACO TCAD tools, specifically known as Athena and Atlas modules. From the observation, the electrical characteristic of 100nm thickness is slightly better than 50nm and 10nm. It is observed that the value drive current of 10nm and 100nm thickness SOI MOSFET was 6.9% and 11% lower than 50nm respectively, but the overall 50nm is superior. However, the electrical characteristics of 10nm SOI MOSFET are still closer and within the range of ITRS 2013 prediction.


MOSFET, Silvaco, drive current, SOI

Full Text:



Mehandia, B. 2012. Study of Electrical Characteristics of SOI MOSFET Using Silvaco TCAD Simulator. 1: 15–18.

Wei, A., Sherony, M. and Antoniadis, D. 1998. Effect of floating-body charge on SOI MOSFET design. IEEE Trans. Electron Devices. 45(2): 430-438.

Veeraraghavan, S. and Fossum, J. 1989. Short-channel effects in SOI MOSFETs. IEEE Trans. Electron Devices. 36(3): 522-528.

Colinge, J. 1988. Reduction of kink effect in thin-film SOI MOSFETs. Electron Device Lett. IEEE. 88–90.

Davis, J., Glaccum, A., Reeson, K., and Hemment, P. 1986. Improved subthreshold characteristics of n-channel SOI transistors. IEEE Electron Device Lett. 7(10): 570-572.

Kumar, A., Kar, N., Jaiswal, A., and Kar, A. 2013. Characterization of SOI PMOSFET using Silvaco TCAD Tools. 2(6): 540–546.

Yoshimi, M., Takahashi, M., Wada, T., Kato, K., Kambayashi, S., Kemmochi, M., and Natori, K. 1990. Analysis of the drain breakdown mechanism in ultra-thin-film SOI MOSFETs. IEEE Trans. Electron Devices. 37(9): 2015-2021.

Kaharudin, K. E., Hamidon, A. H. and Salehuddin, F. 2013. Design and Optimization Approaches in Double Gate Device Architecture. International Journal of Engineering and Technology (IJET). 6(5): 2070-2079.

Salehuddin,F., Ahmad,I., Hamid,F.A., Zaharim,A., Elgomati,H.A., Majlis,B.Y. 2011. Analyze of input process parameter variation on threshold voltage in 45nm n-channel MOSFET. 2011 IEEE Regional Symposium on Micro and Nanoelectronics (RSM 2011). 70-74.

Afifah Maheran A. H., Menon, P. S., Ahmad, I., Shaari, S., Elgomati, H.A., Salehuddin, F. 2013. Design and Optimization of 22 nm Gate Length High-k/Metal gate NMOS Transistor. Journal of Physics: Conference Series. 431(1): 012-026.

ITRS Report 2013. 2013. [Online]. Available: Http:// [Accessed: 27-Feb-2014].

Ferain,I., C. a Colinge, and J.-P. Colinge. 2011. Multigate transistors as the future of classical metal-oxide-semiconductor field-effect transistors. Nature. 479(7373): 310–316.



  • There are currently no refbacks.

Copyright © 2012 Penerbit UTM Press, Universiti Teknologi Malaysia.
Disclaimer : This website has been updated to the best of our knowledge to be accurate. However, Universiti Teknologi Malaysia shall not be liable for any loss or damage caused by the usage of any information obtained from this web site.
Best viewed: Mozilla Firefox 4.0 & Google Chrome at 1024 × 768 resolution.